FAND=0, CAPTDE=00, VALDE=0
DMA Enable Register
| CX0DE | Capture X0 FIFO DMA Enable |
| CX1DE | Capture X1 FIFO DMA Enable |
| CB0DE | Capture B0 FIFO DMA Enable |
| CB1DE | Capture B1 FIFO DMA Enable |
| CA0DE | Capture A0 FIFO DMA Enable |
| CA1DE | Capture A1 FIFO DMA Enable |
| CAPTDE | Capture DMA Enable Source Select 0 (00): Read DMA requests disabled. 1 (01): Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 2 (10): A local sync (VAL1 matches counter) sets the read DMA request. 3 (11): A local reload (STS[RF] being set) sets the read DMA request. |
| FAND | FIFO Watermark AND Control 0 (0): Selected FIFO watermarks are OR’ed together. 1 (1): Selected FIFO watermarks are AND’ed together. |
| VALDE | Value Registers DMA Enable 0 (0): DMA write requests disabled 1 (1): DMA write requests for the VALx and FRACVALx registers enabled |